About Dr. Hamid R. Arabnia

Dr. Hamid R. Arabnia received a Ph.D. degree in Computer Science from the University of Kent (Canterbury, England) in 1987. In 1987, he worked as a Consultant for Caplin Cybernetics Corporation (London, England), where he helped in the design of a number of image processing algorithms that were targeted at a particular parallel machine architecture. Prof. Arabnia is currently a Full Professor of Computer Science at University of Georgia (Georgia, USA), where he has been since October 1987. His research interests include Parallel and distributed processing techniques and algorithms, interconnection networks, and applications (in particular, in image processing, medical imaging, and other computational intensive problems). Prof. Arabnia is the founding chair of WORLDCOMP Congress. He is Editor-in-Chief of The Journal of Supercomputing (Springer) and is on the editorial and advisory boards of 17 other journals and magazines. He is the chair of the world committee of PDPTA (Parallel and Distributed Processing Techniques and Applications research organization: PDPTA is composed of 28 task forces with over 2,800 active participants) and is on the Advisory Board of IEEE Technical Committee on Scalable Computing (TCSC).

Prof. Arabnia is the recipient of William F. Rockwell, Jr. Medal for promotion of multi-disciplinary research (Rockwell Medal is International Technology Institute's highest honor). In 2000, Prof. Arabnia was inducted to the World Level of the Hall of Fame for Engineering, Science and Technology (The World Level is the highest possible level for a living person; since 1982, 41 other individuals have been inducted at this level, including: Allen E. Puckett, CEO of Hughes Aircraft Company; Dr. Robert C. Seamans, Chairman of the board of trustees of Aerospace Corp.; Dr. James C. Fletcher, 7th head of NASA; Dr. Ralph E. Gomory, IBM Director of Research; Dr. Richard M. Cyert, President of Carnegie Mellon University; Dr. John R. Koza, Stanford University; Dr. George M. Reed, Oxford University; Dr. Andrew S. Grove, CEO of Intel Corp.; Dr. Irwin M. Jacobs, CEO of Qualcomm, Inc.; Bill Gates, Chairman of Microsoft Corp.(see http://www.hofest.org/inductee-wlh.asp for the complete list) He has received a number of other awards, including, The Johns Hopkins University National Search in recognition of his contributions to the national program for enhancing the quality of life for people with disabilities through the application of computing technology (presented to him in December 1991 - signatories: co-directors of the National Search and President of Johns Hopkins U.) In 2006, Prof. Arabnia received the Distinguished Service Award in recognition and appreciation of his contributions to the profession of computer science and his assistance and support to students and scholars from all over the world; this award was formally presented to him on June 26, 2006 by Professor Barry Vercoe (Massachusetts Institute of Technology / MIT). Most recently (October 14, 2007), Prof. Arabnia received an "Outstanding Achievement Award in Recognition of His Leadership and Outstanding Research Contributions to the Field of Supercomputing". This award was formally presented to him at Harvard University Medical School (signatories: Lawrence O. Hall, President of IEEE/SMC; Zhi-Pei Liang, Vice President of IEEE/EMB; Jack. Y. Yang, General Chair of IEEE BIBE and Harvard University; Mary Qu Yang, Chair of Steering Committee, IEEE BIBE and NIH). Prof. Arabnia has published extensively in journals and refereed conference proceedings. He has over 250 research publications (journals, proceedings, editorship) in his area of research. Prof. Arabnia has been a Co-PI on $7,139,525 externally funded projects/initiatives (mainly via Yamacraw and includes significant UGA matching) and on $103,453 internally funded projects (as of October 2007). He has also contributed projects for justification for equipment purchase (grant proposals worth over $3 Million - awarded).

A BIO-INSPIRED RECONFIGURABLE COMMUNICATION TOPOLOGY & APPLICATIONS

Inherent limitations on the computational power of sequential uniprocessor systems have lead to the development of parallel multiprocessor systems. The two major issues in the formulation and design of parallel multiprocessor systems are algorithm design and architecture design. The parallel multiprocessor systems should be so designed so as to facilitate the design and implementation of the efficient parallel algorithms that exploit optimally the capabilities of the system. From an architectural point of view, the system should have low hardware complexity, be capable of being built of components that can be easily replicated, should exhibit desirable cost-performance characteristics, be cost effective and exhibit good scalability in terms of hardware complexity and cost with increasing problem size. In distributed memory multiprocessor systems, the processing elements can be considered to be nodes that are connected together via an interconnection network. In order to facilitate algorithm and architecture design, we require that the interconnection network have a low diameter, the system be symmetric and each node in the system have low degree of connectivity. Further, it is also desirable that the system configuration and behavior be amenable to a suitable and tractable mathematical description. The requirement of network symmetry ensures that each node in the network is identical to any other, thereby greatly reducing the architecture and algorithm design effort. For most symmetric network topologies, however, the requirements of low degree of connectivity for each node and low network diameter are often conflicting. Low network diameter often entails that each node in the network have a high degree of connectivity resulting in a drastic increase in the number of inter-processor connection links. A low degree of connectivity on the other hand, results in a high network diameter which in turn results in high inter-processor communication overhead and reduced efficiency of parallelism. Reconfigurable networks attempt to address this tradeoff. In a reconfigurable network each node has a fixed degree of connectivity irrespective of the network size. The network diameter is restricted by allowing the network to reconfigure itself into different configurations. In general, a reconfigurable system needs to satisfy the following criteria in order to be considered practically viable: (a) In each configuration the nodes in the network should have a fixed degree of active connectivity irrespective of network size, (b) The network diameter should be kept low via the reconfiguration mechanism and (c) The hardware for the reconfiguration mechanism (i.e. switch) should be of reasonable complexity.

In this presentation, we discuss our design of a reconfigurable network topology that is targeted at medical applications; however, others have found a number of interesting properties about the network that makes it ideal for applications in computational biology as well as information engineering. We present some results and discuss our ongoing work in this area; time-permitting, we will also present a particular variation to our original reconfigurable network which is nature/biology inspired.

About Professor Laurence T. Yang

Dr. Laurence T. Yang's research includes high performance computing and networking, embedded systems, ubiquitous/pervasive computing and intelligence.
He has published around 300 papers (including around 80 international journal papers such as IEEE and ACM Transactions) in refereed journals, conference proceedings and book chapters in these areas. He has been involved in more than 100 conferences and workshops as a program/general/steering conference chair and more than 300 conference and workshops as a program committee member.

He served as the vice-chair of IEEE Technical Committee of Supercomputing Applications (TCSA) until 2004, currently is the chair of IEEE Technical Committee of Scalable Computing (TCSC), the chair of IEEE Task force on Ubiquitous Computing and Intelligence. He is also in the executive committee of IEEE Technical Committee of Self-Organization and Cybernetics for Informatics, and of IFIP Working Group 10.2 on Embedded Systems, and of IEEE Technical Committee of Granular Computing.
In addition, he is the editors-in-chief of 8 international journals and few book series. He is serving as an editor for around 20 international journals. He has been acting as an author/co-author or an editor/co-editor of 25 books from Kluwer, Springer, Nova Science, American Scientific Publishers and John Wiley & Sons. He has won 5 Best Paper Awards (including the IEEE 20th International Conference on Advanced Information Networking and Applications (AINA-06)); 2 IEEE Best Paper Award, 2007 and 2008; 2 IEEE Outstanding Paper Award, 2007 and 2008; one Best Paper Nomination, 2007; Distinguished Achievement Award, 2005; Distinguished Contribution Award, 2004; Outstanding Achievement Award, 2002; Canada Foundation for Innovation Award, 2003; University Research/Publication/Teaching Award 99-02/02-05/05-07.

Ubiquitous/Pervasive Intelligence: Visions and Challenges

Ubiquitous/Pervasive computers, networks and information are paving a road towards a smart world (SW) in which computational intelligence is distributed throughout the physical environment to provide trustworthy and relevant services to people. This ubiquitous/pervasive intelligence(UI/PI) will change the computing landscape because it will enable new breeds of applications and systems to be developed; the realm of computing possibilities will be significantly extended. By embedding digital intelligence in everyday objects, our workplaces, our homes and even ourselves, many tasks and processes could be simplified, made more efficient, safer and more enjoyable. Ubiquitous or pervasive computing, composes these many "smart things/u-things" to create the environments that underpin the smart world.

In this presentation, the potential trends towards smart world (SW) and ubiquitous/pervasive intelligence (UI/PI) from smart u-things to smart spaces and then to smart hyperspaces will be addressed, as well as, the challenges in smart u-things' research in terms of technical and real world complexity.